/**************************************************************************************

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                                佛祖保佑        永无BUG                                                    

**---------------------------------File Info-------------------------------------------
**                                                                                                        
** @file:               binarization_lx.v
** @author:             LeXin567567
** @date:               2024-06-26
** @brief:              图像二值化
** @problems:    1. post_vsync   ycbcr_hsync  分别是什么意思？  为什么是延时一个时钟周期
**                                                                                                        
**-------------------------------------------------------------------------------------
**************************************************************************************/


module binarization_lx (
    input clk,
    input rst_n,

    input ycbcr_vsync,
    input ycbcr_hsync,
    input ycbcr_de,
    input [7:0] luminance,

    output post_vsync,
    output post_hsync,
    output post_de,
    output reg monoc
);
    
    reg ycbcr_vsync_d;
    reg ycbcr_hsync_d;
    reg ycbcr_de_d;

    assign post_vsync = ycbcr_vsync_d;
    assign post_hsync = ycbcr_hsync_d;
    assign post_de = ycbcr_de_d;

    // Binarization
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) 
            monoc <= 1'b0;
        else if (luminance > 8'd64) 
            monoc <= 1'b1;
        else 
            monoc <= 1'b0;
    end

    // Delay 1 clock to synchronize the clock signal
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
        begin
            ycbcr_vsync_d <= 1'd0;
            ycbcr_hsync_d <= 1'd0;
            ycbcr_de_d <= 1'd0;
        end
        else
        begin
            ycbcr_vsync_d <= ycbcr_vsync;
            ycbcr_hsync_d <= ycbcr_hsync;
            ycbcr_de_d <= ycbcr_de;
        end
    end


endmodule